1. Field of the Invention
The present invention relates to a Secure Hash Algorithm (SHA) operation method, a SHA operation circuit and a hash operation circuit for calculating the hash value of input data.
2. Description of the Background Art
In recent years, there is a growing trend toward hardware implementation of security algorithms for speeding up security processes. Because of this, in many cases, Secure Hash Algorithm (SHA) is implemented with digital operation circuits. The SHA is used in authentication, digital signature and tamper detection and implemented with one of several algorithms, such as SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512.
In this situation, it has been proposed to use a pipeline for performing hash operation at a high speed in a conventional SHA high speed arithmetic circuit, for example, as described in Japanese patent laid-open publication No. 2002-287635.
However, in the case of the conventional circuit, while the hash operation can be speeded up, it is difficult to reduce the power consumption of the hardware which is used for the hash operation. It is therefore necessary to reduce the power consumption of the hardware which is used for the SHA operation.